Electrical engineers at the University of California, Irvine have developed a new wireless transceiver that achieves data speeds comparable to fiber-optic cables. The invention could play a significant role in the shift toward 6G and FutureG data transmission protocols.
The team, based in UC Irvine’s Samueli School of Engineering, designed a silicon chip system that integrates both a transmitter and receiver. Their approach blends digital and analog processing, resulting in faster signal processing and greater energy efficiency than current technologies.
The details of their work are presented in two papers published this month in the IEEE Journal of Solid-State Circuits. One paper focuses on what the researchers call a “bits-to-antenna” transmitter, while the other describes an “antenna-to-bits” receiver.
“We call this technology a ‘wireless fiber patch cord’ because it offers the blistering speed of fiber optics without the physical cables,” said Payam Heydari, director of UC Irvine’s Nanoscale Communication Integrated Circuits Labs and senior author on both papers. “By operating in the F-band – a frequency range well above current 5G standards — we can offer massive bandwidths that will transform how machines, robots and data centers communicate.”
Heydari explained that his team began working on the bits-to-antenna concept in 2020 after recognizing limitations with traditional chip architectures that rely heavily on energy-consuming data converters. “We realized that to reach the elusive 100-gigabit-per-second milestone — which is 100 times the speed of current wireless devices – without melting the chip, we had to fundamentally rethink the circuit topology,” he said. “We envisioned novel, all-analog architectures that could overcome the severe power trade-offs plaguing high-speed designs.”
As device speeds increased, shifting more functions into analog processing helped avoid inefficiencies seen with standard 5G chips. Heydari noted that higher wireless speeds typically require much more power for data processing: “If we stuck to traditional methods, the battery life of next-generation devices would vanish in minutes,” he said. “Our group’s answer is a transceiver that leapfrogs over current limitations by performing complex calculations in the analog domain, rather than the power-hungry digital domain.”
The new transceiver operates at up to 120 gigabits per second—fast enough for transferring multiple ultra-high-definition movies almost instantly.
Zisong Wang, lead author on one paper and former UC Irvine doctoral researcher now at Marvell Technology Inc., highlighted regulatory interest: “The Federal Communications Commission and 6G standards bodies are looking at the 100-gigahertz spectrum as the new frontier,” Wang said. He explained conventional transmitters using digital-to-analog converters (DACs) face complexity and power issues at these frequencies: “But at such speeds, conventional transmitters that create signals using digital-to-analog converters are incredibly complex and power-hungry and face what we call a DAC bottleneck.” The team’s solution constructs signals directly within radio frequencies instead.
Mohammad Oveisi, co-author on one paper and UC Irvine doctoral student, described their method as RF-domain 64QAM—a technique allowing efficient high-speed transmission without overheating devices. This capability is expected to be important for emerging applications like internet-connected products or autonomous vehicles.
Youssef Hassan—lead author on another paper who is now with Qualcomm—explained challenges faced by receivers handling fast data rates: “Traditional receivers struggle to catch such fast data without using massive, energy-draining components called analog-to-digital converters,” he said. While Moore’s law has previously allowed smaller transistors for faster operation, extreme speeds introduce sampling bottlenecks requiring too much power for practical use.
To address this issue instead of increasing hardware demands further, Hassan said they created a smarter receiver design: “We developed a technique called hierarchical analog demodulation,” Hassan explained. “By breaking the signal down hierarchically in the analog domain…we extract the data using a fraction of the power typically required.” The receiver chip uses only about 230 milliwatts—efficient enough for portable electronics.
According to Heydari, beyond enabling operation near 140 GHz frequencies—the architecture also supports mass production at lower cost using routine semiconductor manufacturing processes. This may help reduce wiring needs inside large-scale data centers by replacing copper cabling with ultrafast wireless links between servers.
“Our innovation eliminates the need for miles of complex copper wiring inside data centers,” Heydari said. “Data farm operators can do ultrafast wireless links between server racks, saving considerable money on hardware, cooling and power.”
Funding was provided through support from U.S Department of Defense Microelectronics Commons program.
